This invention generally relates to improved electronic circuitry for performing arithmetic and/or logical operations on multi-bit input operands representing numbers having different radices. More particularly, the invention relates to improved electronic circuitry providing for the performance of BCD and binary arithmetic operations in a digital data processing system.
In a digital data processing system, one of the most critical delay paths affecting overall processing speed is the path through the arithmetic/logic unit (ALU). The primary reasons are:
(1) the ALU is involved in most data processing operations,
(2) an ALU typically involves a complex logical function requiring large numbers of gates, and
(3) the current trend to larger data widths significantly increases carry propagate times even using look-ahead carry circuitry. Furthermore, where an ALU is additionally required to provide both binary and BCD operation, an additional increase in the delay path is to be expected because of the additional gates that would be required to implement the BCD logical functions.
For example, U.S. Pat. Nos. 4,172,288 and 3,958,112 illustrate known ways of providing BCD operation for an ALU. In U.S. Pat. No. 4,172,288, two BCD operands are added by first adding the operands as if they were pure binary numbers to produce an intermediate result. If this intermediate result is greater than nine, a correction value of six is added to obtain the correct BCD result. In U.S. Pat. No. 3,958,112, a reverse approach is employed in which the correction value of six is always added to one of the BCD operands before the operands are added as if they were pure binary numbers. If the intermediate result obtained from this binary addition is less than sixteen, then the correction value of six is subtracted from the intermediate result to obtain the correct BCD result. Although the approaches disclosed in these patents implement the BCD addition, they employ additional gates in a manner which significantly increases the delay of the path through the ALU.
One approach which has been employed in an attempt to reduce the delay of the ALU path when both binary and BCD arithmetic capability are required is disclosed in U.S. Pat. No. 4,441,159 issued Apr. 3, 1984. This approach is basically similar to that disclosed in the aforementioned U.S. Pat. No. 3,958,112 in which a correction value is always added to one of the input operands when a BCD operation is to be performed. In order to avoid the need for an extra stage to provide for addition of the correction value, the embodiment of U.S. Pat. No. 4,441,159 employs a plurality of multiplexers in the ALU input stage in a manner which provides for the addition of a correction value simultaneously with the addition of two input operands so as to produce carry propagate and carry generate signals for each corresponding pair of input operands dependent upon whether BCD or binary addition is to be performed. However, the correction value is added without taking into account any inter-bit carries which may have to be propagated to higher order bits as a result of the addition of the correction value with the input operand bits. As a result, a more complex and slower operating look-ahead carry circuit is required in order to provide an intermediate result which takes all of the inter-bit carries into account, thereby reducing the speed-up benefit achieved using the input multiplexers. Furthermore, the embodiment disclosed in U.S. Pat. No. 4,414,159 also requires extra incrementer stages for use in the event there is an input carry, and also a decimal adjustment stage in order to provide for subtraction of six where necessary to obtain a proper result. These additional stages further increase the delay of the path through the ALU.